Friday, August 26, 2005

Nano Transistors


A Very Large Scale Integrated (VLSI) circuit is a conglomerate of a large number of practically identical, very reliable switches interconnected to express a computing function. The relentless miniaturization of the components that comprise an Integrated Circuit (IC) which has occurred over the last 30 years has been one of the key ingredients to improving performance while reducing cost by a factor of 100,000. Ultimately, it will become uneconomical to produce reliable transistors through miniaturization, however. The figure shows a cross-section through a 35nm gate length MOSFET, a "nano - transistor", obtained using high resolution Transmission Electron Microscope (TEM). The channel length is only about 100 silicon lattice sites long. An enlargement of the channel region delineated by red on the left is shown on the right. The regular array of atoms show in the lower portion of the lattice image corresponds to the single crystal silicon substrate. The gate oxide thickness estimated from the image is only about 1.0nm. The sensitivity to atomic variables is not welcomed by manufacturing


To achieve high performance and high drive current with the low power supply voltage required to minimize power dissipation, the thickness of the gate oxide in sub-100nm CMOS technologies must scale to less than 2nm. However, high resolution Scanning Transmission Electron Microscopy (STEM) used in conjunction with Electron Energy Loss Spectroscopy (EELS) reveals an ultimate physical lower limit to the thickness of about 0.7nm. The figure shows a STEM image of a typical polysilicon/SiO2/silicon gate stack in MOSFET. It shows a regular array of silicon atoms in the substrate, which terminate at the SiO2/Si interface. The chemical constituency of the gate stack and the bonding can be probed by analyzing the energy loss of the transmitted electron beam. We find that a nominally 1.1nm thick oxide has 0.8-1.0nm of bulk SiO2 (blue dashed line) with flanking sub-oxide layers above and below the oxide which are 0.5nm and 0.3nm wide respectively (red dashed line). When the sub-oxide layers coincide, the tunneling barrier associated with the oxide collapses.

Thursday, August 18, 2005

Seminar---Flip Flops

This September 1st I'm going to give a seminar on Flip-Flops.
If any one wanna help me or take help on this related subject please contact me immediately.
Flip-Flops is a basic branch in Digital Design and Communications.
Bye.........Eshwar Prasad

Friday, August 12, 2005

Jokes allround

This time we are gonna see what all the jokes can we collect in this week togather!!
Be ready to get the hot and smooth of all that .Also congratulate tha discovery team for their success.
And at last I request you all to tell me all you know about MEMS/NEMS and free news letters of this.
please do mail me at yaddanapudi1986@gmail.com

Thursday, August 11, 2005

hi

this is eshwar

Sunday, August 07, 2005

Discovery return may it be safe and smooth

Its time that we get our hands togather and pray for God to make the landing of Discovery space shuttle smooth and also to clap for them when they make the landing succeesfully.

Hope we all welcome them with good heart.-----------Eshwar Prasad

Monday, August 01, 2005

NASA space shuttle is scheduled to return on eighth August
The NASA s Discovery space shuttle that is scheduled to come on 7 Aug is now to be on 8th of Aug. to more mail me bbbbbbbbbbbye.